I. Field of the Disclosure
The technology of the disclosure relates generally to bus interconnects for communicatively interfacing diverse electronic systems in processor-based systems.
II. Background
Portable electronic devices, such as mobile phones, personal digital assistants (PDAs), and the like, may be manufactured using application specific integrated circuit (ASIC) designs. Developments in achieving high levels of silicon integration have allowed for creation of complex ASICs and field programmable gate array (FPGA) designs. These ASICs and FPGAs may be provided in a single chip to provide a system-on-a-chip (SOC). An SOC provides multiple functioning subsystems on a single semiconductor chip, such as for example, processors, multipliers, caches, and/or other electronic components. SOCs are particularly useful in portable electronic devices because of their integration of multiple subsystems that can provide multiple features and applications within a single chip. Further. SOCs may provide smaller portable electronic devices with use of a single chip, which may otherwise have been provided using multiple chips.
To communicatively interface multiple diverse components or subsystems within a circuit provided on a chip(s), an interconnect communications bus, also referred to as a bus interconnect, can be provided. The bus interconnect is provided using circuitry, including clocked circuitry, which may include as examples registers, queues, and/or other circuits to manage communications among the various subsystems. The bus interconnect facilitates point-to-point connections between initiators of communications requests and targets of the communications requests. The circuitry in the bus interconnect may be clocked with one or more clock signals generated from a master clock signal that operates at a desired bus clock frequency(ies) to provide a desired throughput.
For applications in which reduced power consumption is desirable, the bus clock frequency may be lowered according to the well-known equation of power consumption being equal to fCV2, where ‘f’ is frequency, ‘C’ is capacitance, and ‘V’ is voltage. However, lowering the bus clock frequency also lowers performance of the bus interconnect. Conversely, lowering the bus clock frequency may increase bus latency beyond latency requirements or conditions for the subsystems coupled to the bus interconnect, in which case the performance of the subsystem may degrade or fail entirely. Rather than incur performance degradation or failure of the subsystem, the bus clock frequency may be set to a higher frequency to reduce latency and provide performance margin. However, providing a higher bus clock frequency for the bus interconnect consumes more power.
In this regard, ring bus architectures may be provided in bus interconnects to enable high speed point-to-point communications with lower power consumption at high bus clock frequencies. FIG. 1 illustrates an exemplary ring bus 10 that may be used to provide a bus interconnect. The ring bus 10 may allow for higher bus clock frequencies due to its use of simpler switches located within ring bus nodes 12(0)-12(15), as compared to a crossbar interconnect. For example, the ring bus nodes 12 illustrated in FIG. 1 may be comprised of a multiplexer (MUX) and a latch (e.g., a D flip-flop). A ring bus architecture implemented in a bus interconnect may also be scalable for chip multi-processor (CMP)-based designs.
With continuing reference to FIG. 1, entry points for communications into the ring bus 10 are provided by transmit ring interface units (Tx RIUs) 14(0)-14(2). Exit points for communications out of the ring bus 10 are provided by receive ring interface units (Rx RIUs) 16(0)-16(1). Bus transaction messages 18 (e.g., 18(0)-18(15)) are advanced around the ring bus 10 on each cycle of a clock 20. In FIG. 1, sixteen ring bus nodes 12 are provided. As a result, up to sixteen bus transaction messages 18 can be communicated on the ring bus 10 at any given time. However, as the number of ring bus nodes 12 increase, latency of point-to-point communications may also increase. To reduce latency in this example, three ring bus nodes 12 have Tx RIUs 14(0)-14(2) attached and two ring bus nodes 12 have two Rx RIUs 16(0)-16(1) attached to provide multiple entry and exit points in the ring bus 10. Even so, a data bus size of the ring bus 10 limits a maximum bandwidth in each communication stage between the ring bus nodes 12. Multiple parallel ring buses 10, each having wide data buses, may be employed to achieve desired bandwidth requirements for higher speed point-to-point connections. However, this leads to higher-power consumption compared to shared buses or crossbar interconnect architectures.